1. Field of the Invention
This invention relates to a semiconductor device, and more particularly, to a multi-chip package-type semiconductor device in which more than one IC chip can be packaged.
2. Description of the Related Art
In the related art, there are several types of multi-chip packages in which more than one IC chip can be packaged. One typical multi-chip package is a stack-type multi-chip package that packages at least two IC chips in a stacked manner.
In the stack-type multi-chip package, the semiconductor device includes an insulating substrate on which conductive patterns are formed, a first semiconductor chip, and a second semiconductor chip mounted on the first semiconductor chip. Each of the semiconductor chips includes terminal pads in a peripheral area on its main surface. An adhesive material is formed on the main surface of the first semiconductor chip except for the terminal pad in order to fix the second semiconductor chip on the first semiconductor chip. More concretely, a back surface of the second semiconductor chip is adhered to a center of the main surface of the first semiconductor chip.
In such a device, after the second semiconductor chip is mounted on the first semiconductor chip, each terminal pad of each of the first and second semiconductor chips is connected to one of the conductive patterns formed on the insulating substrate by a bonding wire so that each semiconductor chip is connected electrically to the insulating substrate. Further, the semiconductor chips and bonding wires are encapsulated by a sealing material, such as a resin.
Therefore, in such a multi-chip package-type semiconductor device, since the second semiconductor chip is directly mounted on the first semiconductor device, the size of the second semiconductor chip should be smaller than that of the first semiconductor chip. That is, the second semiconductor is mounted in the center area of the main surface of the first semiconductor device so that the terminal pads of the first semiconductor device are exposed for connection to bonding wires. Further, the surface of the remainder of the peripheral area also is exposed. Therefore, the size of the second semiconductor chip should not only be smaller than that of the first semiconductor chip, but also be determined by the size of the peripheral area of the first semiconductor chip.
As a result, according to the above described multi-chip package-type semiconductor device, it is almost impossible to stack first and second semiconductor chips having the same size because the first semiconductor chip should have an exposed peripheral area that is not covered by the second semiconductor chips.
To overcome this limitation, some others have been introduced. One typical example is disclosed in Japanese Patent Publication 60-245291. A multi-chip package-type semiconductor device disclosed in that publication includes an insulating substrate having an opening and first and second semiconductor chips stacked with their back surfaces. The first and second semiconductor chips are placed in the opening. In this type of the multi-chip package-type semiconductor device, since the first and second semiconductor chips are connected to each other at their back surfaces, they may be of the same size. However, according to that reference, an adhesive tape are formed on the main surface of one of the semiconductor chips on which a circuit is formed, and then, the adhesive tape is removed for the following steps. Therefore, this step of removing the adhesive tape formed on the circuit may cause damage to the circuit.
It is therefore an object of the invention to resolve the above-described problems in a multi-chip package-type semiconductor device and provide a multi-chip package-type semiconductor device having two stacked, same size semiconductor chips.
The object is achieved by a multi-chip package-type semiconductor device including a first insulating substrate, a second insulating substrate, a first semiconductor chip, a second semiconductor chip of approximately the same size as the first semiconductor chip and bonding wires.
The first insulating substrate includes a first surface and the second surface opposite to the first surface wherein the first insulating substrate has a recess at the first surface. The second insulating substrate includes a first surface and the second surface opposite to the first surface wherein the second insulating substrate further has on the first surface an opening that is larger than the recess, and conductive patterns. Further the second insulating substrate is on the first substrate wherein the opening encompasses the recess. The first semiconductor chip formed in the recess includes a first surface and the second surface opposite to the first surface wherein the first semiconductor chip includes on the first surface a first terminal pad and a first circuit, which is connected to the first terminal pad. The second semiconductor chip includes a first surface and a second surface opposite to the first surface wherein the second semiconductor chip further has on the first surface a second terminal pad and a second circuit, which is connected to the second terminal pad. Further, the second semiconductor chip is supported by the first insulating substrate in an area of the first surface, which is exposed by the opening. The bonding wires connect the first terminal pad to one of the conductive patterns, and for connecting the second terminal pad to another one of the conductive patterns.
The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims and accompanying drawings.